Accompanying fine geometry, high integration, and large capacity of the semiconductor memory devices in recent years, it is becoming extremely difficult to obtain perfect products which are absolutely free from defects. In other words, almost all of the produced semiconductor memory devices include defective memory cells, defective work lines, or defective bit lines. In order to make it possible to deliver semiconductor memory devices that include such defects as acceptable products, it is a general practice to provide the semiconductor memory device with a redundancy circuit.
The redundancy circuit is for disabling the use of a defective word or bit line when there exists one, and replacing the defective word or bit line with a redundant word or bit line. By designing a circuit configuration such that a defective word line or a defective bit line can be replaced by a redundant word line or a redundant bit line, as in the above, it is possible to deliver a semiconductor memory device as if it is absolutely free from defectiveness. Accordingly, a redundancy circuit contributes significantly to the enhancement of the yield of the semiconductor memory devices.
In order to relieve as many defective word lines or defective word lines or defective bit lines as possible, it is most effective to incorporate as many redundant word lines or redundant bit lines as its practicable. However, since the redundancy circuit is a superfluous circuit in the sense that it is useless unless there exists defectiveness in the manufactured semiconductor memory device, it is not recommended to provide a large scale redundancy circuit within the semiconductor memory device. For this reason, it is desirable to relieve as many defective word lines or defective bit lines as possible with a minimum number of redundant word lines or redundant bit lines.
Under those circumstances, a variety of methods for improving the relief efficiency of defective word lines or defective bit lines by means of a redundant circuit have been proposed. As examples, there may be mentioned methods disclosed in U.S. Pat. No. 5,349,556, U.S. Pat. No. 5,355,339, U.S. Pat. No. 5,359,560, and U.S. Pat. No. 5,414,660. The method described in these patents is what is called the row flexible redundancy method. The row flexible redundancy method is a technique for efficiently relieving the word line defects, which has a feature in that the range of replacement covered by one redundant word line is broad.
However, according to the row flexible redundancy method, the relief efficiency for defective bit lines remains unchanged, although the relief efficiency for defective word lines can be improved. Because of this, a method which can also improve the relief efficiency for defective bit lines is in demand.